Dear Readers,
functions and tasks are the very useful features in Verilog/System Verilog. We have been using these features since long in our test bench development.
Though 'function' is available in verilog as well as in System Verilog, there is difference! Now you may want to know what is that difference.
Let me first explain you the differences between task and functions for Verilog language :
Verilog must return a value and a value must be used but In System Verilog If you want to call a function and ignore its return value, you can cast the result to void.
Conclusion :
If you have System Verilog task that does not uses or consume time, we should make it a void function. If you do this, you are free to use this this functions from any task or functions. This is the reason people are using debugging routine as void function rather than a task so that it can be called from any task or function:
For Example:
function void print_value (...........);
$display ("Value of A=%h B=%h C=%h", $time);
endfunction
Here we can see the syntax of usage, $display is not a time consuming feature and at the same time we don't have any other time consuming statements as discussed earlier like delays, blocking statement... This type of function does not need return value to be used. This will ignores returns value.
Hope this is a useful post to understand basic difference between functions and tasks in System Verilog.
Keep Reading & Sharing,
ASIC With Ankit
functions and tasks are the very useful features in Verilog/System Verilog. We have been using these features since long in our test bench development.
Though 'function' is available in verilog as well as in System Verilog, there is difference! Now you may want to know what is that difference.
Let me first explain you the differences between task and functions for Verilog language :
- Tasks can consume time while a function can not which means
- tasks can have delays #50 while functions can not have.
- tasks can also have blocking statements such as @(posedge clock) or wait (xyz) while functions can not have.
- tasks can call functions while reverse case is not allowed (function can not call task)
Verilog must return a value and a value must be used but In System Verilog If you want to call a function and ignore its return value, you can cast the result to void.
Conclusion :
If you have System Verilog task that does not uses or consume time, we should make it a void function. If you do this, you are free to use this this functions from any task or functions. This is the reason people are using debugging routine as void function rather than a task so that it can be called from any task or function:
For Example:
function void print_value (...........);
$display ("Value of A=%h B=%h C=%h", $time);
endfunction
Here we can see the syntax of usage, $display is not a time consuming feature and at the same time we don't have any other time consuming statements as discussed earlier like delays, blocking statement... This type of function does not need return value to be used. This will ignores returns value.
Hope this is a useful post to understand basic difference between functions and tasks in System Verilog.
Keep Reading & Sharing,
ASIC With Ankit
2 comments:
function can also call task
visit the link for detail
http://technicalone.blogspot.in/2013/07/task-called-within-function.html
Thanks for reading the post Soniya.
I saw the example you pointed out. Here is the thing..
- In your example you have used fork 'join_none' which means simulator wont wait for tasks to get finish, it will simply comes out.
If you use join_none process control mechanisum, yes you could use the task inside function.
If you use join_any or simple join for the same thing you would observe errors that you are not allowed to use timing parameters in function.
Meaning, if you want to use timing parameters call inside functions, only way is to use process control "fork join_none" michanisum.
Hope this helps.
Thanks for contributing, Happy reading !
Ankit
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