Sunday, November 30, 2008

System Veriog GOTHCA 01

Dear Readers,

Types defined in different scopes:

The LRM words this as follows: ―The scope of a data type identifier shall include the hierarchical instance scope. In other words, each instance with a user-defined type declared inside the instance creates a unique type. To have type matching or equivalence among multiple instances of the same module, interface, or program, a class, enum, unpacked structure, or unpacked union type must be declared at a higher level in the compilation-unit scope than the declaration of the module, interface, or program, or imported from a package.

This has several implications. For example,

typedef struct {int A; int B;} AB_t;
typedef struct {int A; int B;} otherAB_t;

defines two different types and you cannot simply assign a variable of one type to a variable of the other, even though the type contents are identical. You must use an explicit type cast. GOTCHA!

Furthermore, if the type declaration of AB_t is found in module m, and m is instantiated twice, as m1 and m2, then the two types m1.AB_t and m2.AB_t are considered different types and again cannot be assigned from one to the other without an explicit cast.

However, if the typedef is found at a higher level, such as in the compilation-unit scope of the module ($unit), or in a package that is imported into the module, then the two module instances are considered to have the same type definition.

An anonymous type declaration also defines its own type. An anonymous type declaration is where the type definition appears as part of the variable declaration, and not as a separate typedef. For example:

struct {bit[15:0] value;} AB4, AB5;
struct {bit[15:0] value;} AB6;

AB4 and AB5 are defined with the same anonymous type declaration, and so they are assignment-compatible, but AB6 has a separate anonymous type definition and thus is not assignment-compatible with AB4 and AB5 without a cast, even though the type definitions are identical.

As stated in the LRM, these restrictions apply to enums, unpacked structures and unions, and classes. So they do not apply, for example, to packed structs or to arrays, packed or unpacked.

So a function can return an unpacked struct, for example, but you won‘t want to define the struct as an anonymous type in the function header, like this:

function struct {bit[15:0] value;} f(args);

because then you will not be able to assign the function return value to another variable in the calling scope, as they will be considered to have different types:

AB4 = f(args); // illegal, different types

Hope this is useful information.

Happy Reading,
ASIC With Ankit

Verilog Gotcha 02

Dear Readers,

Most of us have gotten used to the idea that numerical operands in an expression are size-extended to the size of the widest operand. We are less used to it with respect to strings, and it can hit us when we least expect it.

One particular case where it is easy to forget size-extension is in the conditional operator. If we write

cond ? expr1 : expr2

then the shorter expression of expr1 and expr2 is extended to the size of the wider one. But suppose we have something like this:

integer file; file = $fopen({"filename", dat1 ? ".dat1" : ".dat"}) ;

In this contrived example, we concatenate a file extension .dat1 or .dat to the given filename, where a variable called dat1 tells us the type of the file. If the variable dat1 is true, there is no problem, we open a file named ―filename.dat1, but if dat1 is false, then we try to open a file called ―filename .dat, with a space before ―.dat, which is extended to the size of ―.dat before being concatenated to ―filename. GOTCHA!

Actually, the shorter string literal is not extended with a space character, which is x20 ASCII, but rather with zeroes (zero-extension), which are null characters.

However, when used as a string, this often becomes a space. Note that if we had assigned the concatenation to a variable of string type, this would not occur.

string temp;
temp = {"filename", dat1 ? ".dat1" : ".dat"} ;
file = $fopen(temp) ;

The shorter string literal would still be zero-extended. However, upon assignment to string variables, null-characters are ignored, so ―.dat would still be appended directly to ―filename.

Wednesday, October 8, 2008

USB 3.0 : 27GB data transfe can hapens in 70 seconds...

I am a great fan of USB 3.0, so my views are biased. I just don’t want the critics beating up USB because they expected.
The USB 3.0 Promoters are targeting a 350 Megabytes per second effective throughput for USB 3.0. This is 10x faster than the effective throughput of USB 2.0 (about 32 Megabytes per second).

The actual signalling rate of USB 3.0 is actually higher, something like 600 Megabytes per second, however, because of the protocol overhead, hardware, device, operating system, and driver latencies, the effective throughput lower. This is true of all devices you and I own today, not just USB. It is the reason why USB 2.0 goes at 350 Megabits per second of effective throughput instead of 480 Megabits per second (again the electrical signalling rate). Of course, the USB 3.0 Promoters are doing everything they can to minimize this.

What would be the first Consumer product with USB3.0?
I know what the first USB 3.0 Consumer Products should be.

The Digital Camcorder.
The Camcorder will have a hard drive (like a laptop drive) and will likely shoot high definition. It will have a 80 GB drive minimum, and will sell for $800-$1000. This targets the Prosumer market, the people that are used to paying $800 or more for a camcorder. They are serious enough that, today, these people already either use tapes and take the 1 hour to transfer and another 1 hour to convert these to an MPEG file. Or they do nothing and accumulate the tapes.

With USB 3.0, you will be able to transfer 27GB of data in about 70 seconds.

This makes a new business viable. For example, for digital still cameras, at CostCo or other places, you can plug in you photo memory card, and print pictures. If you want to print all, the process is less than 3 minutes of transfer and checkout. Then you just shop and pick up your photos after you check-out. This is not viable with todays tapes or USB 2.0 speeds.
With Super Speed USB, you will be able to drop off your camera with the attendant, pick you DVD menu, and when you check out you will have a DVD (or Blu-Ray Disk) with your videos. This makes shooting video much, much more compelling that today’s process.

Power in USB2.0 Device

More devices are doing more things. The best example of devices that have more functions are phones.
Anyone shopping for a mobile phone, will see that the newest phones have more and more functions. Since the introduction of the iPhone, every company is introducing larger screens and touchscreens. The larger screens require more power to operate. More software to run more applications. More software to manage all the applications. More software to manage the power for the applications. More software to manage when the WiFi and Bluetooth are on-and-off. A touch screen that is polling all the time for data from the touch screen. And, in the case of the iPhone, an accelerometer that senses motion (like turning the phone to view pictures in the correct perspective. For a camera phone, an image capture device and maybe even a flash.
All these feature require power. Product makers must manage battery life or be doomed to 30 minutes of talk time. So the choices for managing are:

1) Design the chip hardware to consume less power2) Design the software to manage power usage for each application3) Make the battery bigger to provide more juice4) Accept shorter battery life

3) Bigger batteries - The iPhone is larger both because of the screen, and probably to house a larger battery. Battery life is always relative to some other device. For example, my Blackberry would probably run for 2 weeks as a phone, but once I add data, it’s probably 1 week, and with Bluetooth, maybe 6-7 hours of talk time, and it has to be recharged.

For 1) Change the hardware, we have done some studies with interesting results.Some research indicates that for some companies aggressively implementing hardware features to reduce power are nearing their limits. Phone companies are probably in the lead here.

If you really implement these features, you can squeeze out some extra battery life.
For me, the most interesting thing is that a lot of companies still do not employ these methods. These are consumer devices. There is still room on the hardware side by using our Low Power Methodology Manual. This is absolutely clear, however, you must implement multiple power domains, multiple power rails, and MTCMOS, among other things. Because of the time and effort required, many companies do not even attempt this.

This means
A) Implement simpler hardware options for reducing power

What does this have to do with USB?
The fastest, easiest hardware solution is to use HSIC to implement add-on USB functions. HSIC uses a PHY that is 1/3 the power and area of a standard USB PHY. If you add the USB standard Link Power Management, LPM, you add the hardware capability to use LPM. (This is the USB standard LPM). Add the software for LPM and you can save a lot of power, possibly up to 20% of your battery life can be recovered depending on the kind of USB device you are using.

Monday, September 15, 2008

SONY was started with $190 only, in 1946

Can you believe this.. ? SONY Electronics, Japan based company was started with a seed capital of $190. Today Sony Corporation has a market capitalization value of arounf $41 bilion.

Sony's hystory can be credited to Morita's (Akio Morrita) crearivity and innocative ideas. His ideas gave birth to totally new lifestyles and cultures. In 1949 company developed magnatic tape and 1950 they have sold first tape recorder in Japan. In 1957 they have produced a pocket size radio. Then in 1960 Sony produces first transistor television in the world, In 1979 the walkman was introduced to world making it to worlds first portable music player. In 1984 Sony launches the Discman series which extended their Walkman brand to portable CD products.

How Sony was started ?

After studying Physics in college, Akio joined Japanes army during the World War where he met, masura Ibuka. They formed the company which later know as Sony Corporation.

Saturday, September 13, 2008

Full ASIC Design Flow

As an ASIC Engineer, we should have idea about the whole ASIC design and verification flow. Here I have described all the useful steps which must be follow start from the thinking of the Micro architecture to the Fabrication of the Chip.

I hope this information will be useful as an ASIC Engineer. Please leave your comments or question if you have any. I will try my best to reply you soon.

Step 1: Create an Micro-Architecture Document.

Step 2: RTL Design & Development of IP's

Step 3: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.
Step 3a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL
Step 3b: Perform Property Checking , to verify the RTL implementation and the specification understanding is matching.

Step 4: Prepare the Design Constraints file (clock definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)

Step 5: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain.

6: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis.
Step 6a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets.
Step 6b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements.
Step 6c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality.
Step 6d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements.
Step 6e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement.

Step 7: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Actitivities.

Step 8: The next step is the Floor-planning, which means placing the IP's based on the connectivity,placing the memories, Create the Pad-ring, placing the Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements(Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related acitivities, creating an optimised floorplan, where the design meets the utilization targets of the chip.
Step 8a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring .
Step 8b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements.The power-grid is built to meet the power-target's of the Chip .

Step 9: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement.

Step 10: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is generated.

Step 11: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step.
Step 11a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets.
Step 11b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement .
Step 11c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality.
Step 11d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements.
Step 11e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Peform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors.
Step 11f: Convert the ATPG test-vector to a tester understandable format(WGL)
Step 11g: Perform DRC(Design Rule Check) verfication called as Physical-verification, to confirm that the design is meeting the Fabrication requirements.
Step 11h: Perform LVS(layout vs Spice) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching.
Step 11i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement.
Step 11j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have seperate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise.
Step 11k: Perform seperate STA(Static Timing Analysis) , to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design.
Step 11l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits.

Step 12: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 13: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file.

Step 14: After the GDS file is released , perform the LAPO check so that the database released to the fab is correct.

Step 15: Perform the Package wire-bonding, which connects the chip to the Package.

What is ASIC (Application Specific Integrated Ckt)

what is ASIC ?

ASIC stands for the abbreviation of Application Specific Integrated Circuits. It means an integrated circuit designed for a specific application. An application could be a microprocessor, cell phone, modem, router, etc., The respective ASIC will have its own architecture, need to support its own protocol requirements . In todays ASIC has a complete system in a single often called as System on a Chip(SOC).

The flow involved to achieve this could be semi custom or full custom. The various cost function for an ASIC chip could be "Area, Timing, Power" Targets.
Basically microprocessor involves full custom. Full custom designs take lot of time to design. Full custom designs are used to achieve high frequency targets.
Where as in a semi custom flow, initially the standard cells are pre designed based on the characterization of the silicon for a specific process.